Microelectronic devices are small, complex electronic devices manufactured on a substrate made from glass or a suitable semiconductive material (e.g., silicon) on a suitable insulating material (e.g., glass). A typical microelectronic device has many small components formed in multiple layers of materials. One type of microelectronic device particularly relevant to the present invention is a field emission display ("FED").
FEDs are one type of flat panel display in use or proposed for use in computers, television sets, camcorder viewfinders, and a variety of other applications. FEDs have a baseplate with a generally planar emitter substrate juxtaposed to a faceplate. FIG. 1 illustrates a portion of a conventional FED baseplate 20 with a conductive emitter substrate 30, and a number of emitters 32 formed on the emitter substrate 30. An insulator layer 40 made from a dielectric material is disposed on the emitter substrate 30, and an extraction grid 50 made from polysilicon is disposed on the on the insulator layer 40. A number of cavities 42 extend through the insulator layer 40, and a number of holes 52 extend through the extraction grid 50. The cavities 42 and the holes 52 are aligned with the emitters 32 to open the emitters 32 to the faceplate (not shown).
Referring to FIGS. 1 and 2, the emitters 32 are grouped into discrete emitter sets 33 in which the bases of the emitters 32 in each set are commonly connected. As shown in FIG. 2, for example, the emitter sets 33 are configured into rows (e.g., R.sub.1 -R.sub.3) in which the individual emitter sets 33 in each row are commonly connected. Additionally, each emitter set 33 has a grid structure superjacent to the emitters that is configured into columns (e.g., C.sub.1 -C.sub.2) in which the individual grid structures are commonly connected in each column. Such an arrangement allows an X-Y addressable array of grid-controlled emitter sets. The two terminals, comprising the emitters and the grids, of the three terminal cold cathode emitter structure (where the third terminal is understood to be the anode disposed on the faceplate [not shown in FIG. 2]) are commonly connected along such rows and columns, respectively, by means of high-speed interconnects. The interconnects 60 (also shown in FIG. 1) are formed on top of the emitter substrate 30 and the extraction grid 50, and they serve to electrically connect the individual grid structures forming the columns. It will be appreciated that the column and row assignments were chosen for illustrative purposes and can be exchanged with no loss of intellectual content.
In operation, a specific emitter set is selectively activated by producing a voltage differential between the extraction grid and the specific emitter set. A voltage differential may be selectively established between the extraction grid and a specific emitter set through corresponding drive circuitry that generates row and column signals that intersect at the location of the specific emitter set. Referring to FIG. 2, for example, a row signal along row R.sub.2 of the extraction grid 50 and a column signal along a column C.sub.1, of emitter sets 33 activates the emitter set at the intersection of row R.sub.2 and column C.sub.1. The voltage differential between the extraction grid and the selectively activated emitter sets produces localized electric fields that extract electrons from the emitters in the activated emitter sets.
The display screen of the faceplate (not shown) is coated with a substantially transparent conductive material to form an anode, and the anode is coated with a cathodoluminescent layer. The anode, which is typically biased to approximately 1.0-2.0 kV, draws the extracted electrons through the extraction grid and across a vacuum gap (not shown) between the extraction grid and the cathodoluminescent layer of material. As the electrons strike the cathodoluminescent layer, light emits from the impact site and travels through the anode and the glass panel of the display screen. The emitted light from each of the areas becomes all or part of a picture element.
One manufacturing concern with FEDs is that conventional interconnects may contact irregular, oversized protuberances located under the interconnects. Referring to FIG. 1, the interconnect 60 is conventionally formed on top of a polysilicon extraction grid 50 after the extraction grid 50 and the underlying insulator layer 40 have been planarized with a chemical-mechanical planarization ("CMP") process. A large, irregular protuberance 34 may extend to the top surface 54 of the extraction grid 50 that was created by the CMP process. As shown in FIG. 1, when the defective protuberance 34 is formed under the metal interconnect 60, the defective protuberance 34 creates a short between the interconnect 60 and the emitter substrate 30. Thus, it would be desirable to develop a baseplate and a process for making a baseplate in which the interconnects are electrically isolated from protuberances that can short the interconnect to the emitter substrate.
Another manufacturing concern with FEDs is that a voltage drop occurs across the extraction grid at each emitter set. Referring to FIG. 1, a voltage drop occurs from a point P to a point C on the extraction grid 50 because polysilicon is reasonably resistive. As a result, the emitters 32 located at the center of the emitter set 33 experience a lower potential and may emit fewer electrons than those at the perimeter of the emitter set 33. Therefore, it would be desirable to reduce the voltage drop across the extraction grid.
Still another manufacturing concern with FEDs is that several process steps are required to fabricate a conventional baseplate. In a conventional process, a baseplate is fabricated by:
(1) forming emitters on a silicon emitter substrate; PA1 (2) depositing an oxide insulating layer over the emitters; PA1 (3) depositing a polysilicon layer over the oxide layer to provide material for an extraction grid; PA1 (4) planarizing the polysilicon layer and the oxide layer to form a polysilicon extraction grid with holes over the emitters, and to expose the portions of the oxide layer in the holes; PA1 (5) patterning the polysilicon layer forming distinct addressable lines; PA1 (6) depositing and patterning a metal layer over the planarized polysilicon extraction grid to form interconnects on the extraction grid; and PA1 (7) etching cavities in the oxide layer through the holes in the extraction grid and adjacent to the emitters to open the emitters to the holes in the extraction grid.
It will be appreciated that reducing the number of processing steps reduces the time and material costs to produce FEDs. Thus, it would also be desirable to reduce the number of steps to fabricate a baseplate.
In light of the manufacturing concerns with conventional FED baseplates and the conventional processes for fabricating baseplates, it would be desirable to develop an FED baseplate in which the interconnects are electrically isolated from protuberances under the interconnects that may project from the emitter substrate. It would further be desirable to reduce the voltage drop across an FED extraction grid at each emitter set, and to produce an FED baseplate in fewer steps.